Many of today's commercial integrated circuit (IC) devices and multi-chip modules (MCM) cannot be utilized in deep space and earth orbiting applications because of Total Dose radiation induced damage. Commercial IC devices are developed and manufactured for the computer and mass market applications and are not designed to withstand the effects of the natural space environment. The type and source of radiation in space include solar flares, galactic cosmic radiation and the Van Allen trapped electron and proton belts or man-made radiation induced events (neutrons and gamma radiation).
Commercially available metal packaged integrated circuits and multi-chip modules have not been used in spacecraft applications because of both perceived and real reliability problems. Some examples of commercial multi-chip modules are U.S. Pat. Nos. 5,578,526, 5,502,289, 5,495,389, 5,495,394, 5,436,411, 5,422,435. The major issues needing to be addressed for commercial integrated circuits in order for them to fly in space are the reliability and survivability of these devices when exposed to spacecraft environmental hazards such as total dose levels of electrons, protons, solar flares, and cosmic radiation. Typical silicon integrated circuit plastic, ceramic, metal and multi-chip module packaged devices will fail to operate when exposed to total doses of 2 to 15 Krads(Si). Since communication satellites are expected to function in orbit for periods of 18 to 15 years, this would rule out almost all commercially available packaged silicon integrated circuit devices and multi-chip modules.
Common methods used to prevent radiation degradation in performance for integrated circuits are: 1) design special radiation tolerant die, 2) screen each part for radiation tolerance, or 3) shield package or the platform. There are tradeoffs with each of these methods. The first example usually is the most radiation tolerant. Here the die is specially designed to be radiation tolerant. However, this method is both time consuming and expensive to produce since the part must be redesigned to incorporate radiation hardening techniques. Examples of this method include U.S. Pat. Nos. 5,324,952, 5,220,192, 5,140,390, 5,024,965, 5,006,479, 5,001,528, 4,903,108, 4,825,278, 4,675,978, 4,402,002, 4,313,7684, 4,148,049,4,014,772, and 3,933,530. This method delays the time to market such that these radiation hardened devices are usually 2 to 3 generations behind the current commercial technological advances in both size and capabilities. There are additional penalties in limited marketability and demand for the product. The result is a higher cost from low volume productions of the die. The end result, is that this method produces; 1) a more expensive product that is 2) technologically behind current commercially available microelectronics, 3) frequently with slower speed and 4) less capability. Additionally because of the limited market for these products, frequently they are not available at all.
The second method involves testing each part or die lot in the hopes that the die will meet the mission radiation requirements. This could be an expensive process because of the large amount of testing that would be required and the low probability of success in finding an inherently radiation tolerant die that meets the mission requirements. This problem is compound for Multi-chip Modules in that all the die required in the package need to be radiation tolerant. This is not only extremely restrictive on the design and expensive because of the amount of testing but it is highly unlikely that all the required die will be found that will meet the radiation requirements of the mission.
The third method involves shielding the part. This method includes either shielding the entire satellite, subsystem or individual part. Shielding the satellite or subsystem carries extreme weight and size penalties that generally make this solution cost prohibitive. The spacecraft has some inherent shielding the skin and spacecraft components, however this is very difficult to model and generally doesn't provide adequate shielding for all parts and directions.
An example of system level shielding is U.S. Pat. No. 4,833,334, which is incorporated by reference as if fully set forth herein, describes the use of a protective box to house sensitive electronic components. This box is partially composed of a high atomic weight material to effectively shield against x-rays. However this approach has the serious disadvantage off adding substantial bulk and weight to electronic circuit assemblies protected in this manner. Moreover, it would be expensive to provide this type of protection to individual integrated circuits as manufacturing custom boxes for each circuit configuration would be costly. Similarly U.S. Pat. No. 5,324,952, follows a method of shielding components. If shielding is required the better method is to shield only the components that require shielding.
One method of shielding individual components is know as spot shielding. With this method, a small shield is attached to the surface of the package. However this method does not provide effective 3-dimensional shielding protection. Additionally, the external shield is generally thermally mismatched to the package, and increases the size and weight of the package. Often a bottom spot shield cannot be used due to the inability to accommodate a fixed lead length. The spot shield also has no mechanical support except the adhesive used to attach it to the surface of the package.
An example of spot shielding is disclosed in Japanese patent publication 62-125651, published Jun. 6, 1987 which is incorporated by reference as if fully set forth herein. This patent describes a spot shielded semiconductor device which utilizes a double layered shield film to a sealing cover on an upper surface of the semiconductor package and attaching another double layered shield film to a lower surface of the package. However, space qualified microelectronic parts must be capable of withstanding the enormous forces exerted during acceleration periods. The external shields are subject to tearing or prying off from the sealing cover. The use of a double layer shield film only slightly reduces the weight of the package but increases the size of the package unnecessarily. Also thin films are generally only effective at shielding Electromagnetic Interference (EMI) radiation and are ineffective at shielding ionizing radiation found in space. Examples of this type of EMI or EMF shielding devices include U.S. Pat. Nos. 4,823,523, 4,868,716 and 4,266,239.
The significant disadvantage of the spot shielding method include an increase in weight and thickness of the device, an increase in exposure of the semiconductor to side angle radiation due to the shielding being spaced apart from the semiconductor.
A better method of shielding involves using an integrated shield, where the package itself is the shield. The best example of this is Space Electronics Inc.'s RAD-PAK.RTM. technology, patent application Ser. No. 08/372,289 where the material in the package and the package design is optimized for the natural space radiation environment. However this method focuses on single-sided MCMs and monolithic ICS. These designs are acceptable for most applications but do not maximize the density of integrated circuit designs.
The inventions described herein will provide:
Improved shielding in all axial directions PA1 Ability to take advantage of current generation IC technological advances PA1 Lower cost due to PA1 Improved Delivery times PA1 Higher density of integrated circuits
The use of commercially available dies at market prices
In addition, the inventions are improvements to patent application Ser. No. 08/372,289, titled Radiation Shielding of Integrated Circuits and Multi-Chip Modules in Ceramic and Metal Packages. These designs provide 3-dimensional techniques which result in lighter and more dense Multi-Chip modules (MCMs). Several new design approaches are described, each with its attendant advantages and cost/performance characteristics.